NXP T2080 Port Refresh

[dgarske]

NXP T2080 Port Refresh

• Initial port refresh for the NXP T2080 target
• IFC Flash driver and multi-core support on T2080
• Working wolfBoot test-app startup on T2080
• Support for multiple T2080 vendor boards

[Copilot]

Pull request overview

Refreshes the NXP T2080 (e6500) port by updating early boot/MMU bring-up, moving RAMFUNCTION code into CPC SRAM before DDR init, adding DDR stack relocation, and expanding platform/flash support.

Changes:

• Add e6500-safe address loading, CPC SRAM init/release path, early UART checkpoints, and DDR stack switch.
• Rework T2080 HAL: split SoC definitions into nxp_t2080.h, add DDR init improvements, flash erase/program support, MP spin-table boot, and DTS fixups.
• Update linker script/config/docs and build flags to match the new memory layout and tooling.

Reviewed changes

Copilot reviewed 13 out of 13 changed files in this pull request and generated 8 comments.

Show a summary per file

File	Description
src/boot_ppc_start.S	Adds e6500-safe address loads, early UART macros, CPC SRAM sequence changes, DDR stack trampoline, and ISR dump behavior.
src/boot_ppc_mp.S	Fixes linear core ID calc and adds temporary CCSR TLB for secondary cores on e6500.
src/boot_ppc.c	Copies .ramcode early (pre-DDR), flushes caches, and switches stack to DDR before main().
include/wolfboot/wolfboot.h	Extends RAMFUNCTION attribute behavior for PPC.
hal/nxp_t2080.ld	Changes RAM to 1MB CPC SRAM and introduces .ramcode placement/copy symbols.
hal/nxp_t2080.h	New SoC/board header consolidating T2080 register and DDR/IFC/UART definitions.
hal/nxp_t2080.c	Major HAL rewrite: DDR init, CPC release-to-cache, flash ops, MP bring-up, DTS fixups.
hal/nxp_ppc.h	Updates target config, adds early UART helper, corrects SPR defs for e6500, and adjusts asm set_tlb for 64-bit MAS.
docs/Targets.md	Updates T2080 documentation/config guidance and sample output.
config/examples/nxp-t2080.config	Updates example config for CPC SRAM + RAM_CODE and new flash/partition settings.
config/examples/nxp-t2080-68ppc2.config	Removes legacy per-board config file.
arch.mk	Adds PPC freestanding flags, target CPU flags, forces DEBUG_UART for T2080, and includes MP object.
.github/workflows/test-configs.yml	Removes CI build job for the deleted 68ppc2 config.

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[Copilot]

Pull request overview

Copilot reviewed 13 out of 13 changed files in this pull request and generated 5 comments.

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[Copilot]

Pull request overview

Copilot reviewed 13 out of 13 changed files in this pull request and generated 4 comments.

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[Copilot]

Pull request overview

Copilot reviewed 13 out of 13 changed files in this pull request and generated 4 comments.

Comments suppressed due to low confidence (1)

src/boot_ppc_start.S:1

• This changes the controlling macro from CACHE_SRAM_ADDR to L1_CACHE_ADDR. If other PPC targets (or existing configs) still define CACHE_SRAM_ADDR but not L1_CACHE_ADDR, they will silently skip cache_sram_init. Consider supporting both (e.g., #if defined(L1_CACHE_ADDR) || defined(CACHE_SRAM_ADDR) with an alias) to avoid a cross-target regression.

/* boot_ppc_start.S

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Pull request overview

Copilot reviewed 16 out of 16 changed files in this pull request and generated 5 comments.

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