icarus-verilog

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Here are 100 public repositories matching this topic...

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Feb 18, 2026
Python

dpretet / async_fifo

Sponsor

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Feb 13, 2026
Verilog

mshr-h / vscode-verilog-hdl-support

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HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Mar 2, 2026
TypeScript

wyvernSemi / pcievhost

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PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Mar 3, 2026
C

stnolting / neorv32-verilog

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♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Dec 3, 2025
VHDL

scarv / xcrypto

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XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

unixb0y / SystemVerilogSHA256

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SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

dpretet / svut

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SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

sgherbst / svreal

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Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

albertxie / iverilog-tutorial

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Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

wyvernSemi / usbModel

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USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

usb vhdl verilog vivado systemverilog icarus-verilog ghdl nvc xsim cosimulation cmodel questa-sim

Updated Oct 15, 2024
C++

yasnakateb / PipelinedARM

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💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

wyvernSemi / tcpIpPg

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10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

simulation verification verilog vivado ethernet icarus-verilog ghdl tcp-ip verilator nvc 10g xsim virtual-processor xgmii questa-sim

Updated Jan 28, 2025
C++

sifferman / fusesoc_template

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Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Updated Jul 25, 2021
Python

aditeyabaral / DDCO-Lab-UE18CS207

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A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

yasnakateb / NoCRouter

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🎞️ NoC router in Verilog with FIFO

router verilog icarus-verilog verilog-hdl iverilog

Updated Sep 1, 2022
Verilog

Varunkumar0610 / RISC-V-32I-5-stage-Pipeline-Core

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Implementation of 5 Stage 32I RISC V Pipeline Processor.

pipeline visual-studio-code riscv verilog icarus-verilog gtkwave

Updated Sep 6, 2024
Verilog

Elphel / vdt-plugin

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mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

esynr3z / pyhdlsim

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Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

Alfredosavi / tangnano-hello

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Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Updated Jul 26, 2024
Makefile

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icarus-verilog

Here are 100 public repositories matching this topic...

olofk / edalize

dpretet / async_fifo

mshr-h / vscode-verilog-hdl-support

wyvernSemi / pcievhost

stnolting / neorv32-verilog

scarv / xcrypto

unixb0y / SystemVerilogSHA256

dpretet / svut

sgherbst / svreal

albertxie / iverilog-tutorial

wyvernSemi / usbModel

yasnakateb / PipelinedARM

wyvernSemi / tcpIpPg

sifferman / fusesoc_template

aditeyabaral / DDCO-Lab-UE18CS207

yasnakateb / NoCRouter

Varunkumar0610 / RISC-V-32I-5-stage-Pipeline-Core

Elphel / vdt-plugin

esynr3z / pyhdlsim

Alfredosavi / tangnano-hello

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