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fix[libcpu][risc-v]: mmu pte configuration #11229

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Merged
Rbb666 merged 3 commits into from
Feb 26, 2026
+118 −18
Merged

fix[libcpu][risc-v]: mmu pte configuration #11229

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2b39edd
fix[libcpu][risc-v]:
goodnorning Feb 26, 2026
667b0ce
fix[bsp][xuantie]: Add RISC-V Standard Svpbmt Extension macro definit…
goodnorning Feb 26, 2026
85d28df
fix[bsp][ultrarisc]: Add RISC-V Standard Svpbmt Extension macro defin…
goodnorning Feb 26, 2026
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12 changes: 12 additions & 0 deletions bsp/ultrarisc/arch/ur-cp100/riscv_mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,18 @@

#undef PAGE_SIZE

/*
* RISC-V Standard Svpbmt Extension (Bit 61-62)
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
* 01: NC (Non-cacheable, Weakly-ordered)
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
* 11: Reserved
*/
#define PTE_PBMT_PMA (0UL << 61)
#define PTE_PBMT_NC (1UL << 61)
#define PTE_PBMT_IO (2UL << 61)
#define PTE_PBMT_MASK (3UL << 61)

#define PAGE_OFFSET_SHIFT 0
#define PAGE_OFFSET_BIT 12
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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12 changes: 12 additions & 0 deletions bsp/xuantie/virt64/c906/libcpu/riscv_mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,18 @@

#undef PAGE_SIZE

/*
* RISC-V Standard Svpbmt Extension (Bit 61-62)
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
* 01: NC (Non-cacheable, Weakly-ordered)
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
* 11: Reserved
*/
#define PTE_PBMT_PMA (0UL << 61)
#define PTE_PBMT_NC (1UL << 61)
#define PTE_PBMT_IO (2UL << 61)
#define PTE_PBMT_MASK (3UL << 61)

#define PAGE_OFFSET_SHIFT 0
#define PAGE_OFFSET_BIT 12
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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12 changes: 9 additions & 3 deletions libcpu/risc-v/common64/mmu.c
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Expand Up @@ -740,12 +740,18 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)

static int _noncache(rt_ubase_t *pte)
{
return 0;
*pte &= ~PTE_PBMT_MASK;
*pte |= PTE_PBMT_NC;
rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
return RT_EOK;
}

static int _cache(rt_ubase_t *pte)
{
return 0;
*pte &= ~PTE_PBMT_MASK;
*pte |= PTE_PBMT_PMA;
rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
return RT_EOK;
}

static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_ubase_t *pte)=
Expand Down Expand Up @@ -829,7 +835,7 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
attr = MMU_MAP_K_RWCB;
break;
case NORMAL_NOCACHE_MEM:
attr = MMU_MAP_K_RWCB;
attr = MMU_MAP_K_RW;
break;
case DEVICE_MEM:
attr = MMU_MAP_K_DEVICE;
Expand Down
68 changes: 65 additions & 3 deletions libcpu/risc-v/t-head/c906/riscv_mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,31 @@

#undef PAGE_SIZE

/* C-SKY extend */
#if !CONFIG_XUANTIE_SVPBMT
/*
* RISC-V Standard Svpbmt Extension (Bit 61-62)
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
* 01: NC (Non-cacheable, Weakly-ordered)
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
* 11: Reserved
*/
#define PTE_PBMT_PMA (0UL << 61)
#define PTE_PBMT_NC (1UL << 61)
#define PTE_PBMT_IO (2UL << 61)
#define PTE_PBMT_MASK (3UL << 61)
#else
/* XuanTie Extension (Bit 59-63) */
#define PTE_SEC (1UL << 59) /* Security */
#define PTE_SHARE (1UL << 60) /* Shareable */
#define PTE_BUF (1UL << 61) /* Bufferable */
#define PTE_CACHE (1UL << 62) /* Cacheable */
#define PTE_SO (1UL << 63) /* Strong Order */
/* Compatible with Standard Svpbmt */
#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
#endif

#define PAGE_OFFSET_SHIFT 0
#define PAGE_OFFSET_BIT 12
Expand Down Expand Up @@ -65,11 +84,20 @@
#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
#define PAGE_ATTR_DEV (PTE_SO)

#if !CONFIG_XUANTIE_SVPBMT
/*
* Default Leaf Attribute:
* RWX + User + Valid + Global + Accessed + Dirty + PMA(Cacheable)
*/
#define PAGE_DEFAULT_ATTR_LEAF \
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
#else
#define PAGE_DEFAULT_ATTR_LEAF \
(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
PAGE_ATTR_RWX | PTE_V)
#define PAGE_DEFAULT_ATTR_NEXT \
(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
#endif

#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)

#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)

Expand All @@ -89,6 +117,38 @@
#define ARCH_VADDR_WIDTH 39
#define SATP_MODE SATP_MODE_SV39

#if !CONFIG_XUANTIE_SVPBMT
/*
* Kernel Mappings
*/
/* Device: IO Mode (Strongly Ordered) */
#define MMU_MAP_K_DEVICE (PTE_PBMT_IO | PTE_A | PTE_D | PTE_G | PTE_W | PTE_R | PTE_V)

/* RW: Non-Cacheable (NC Mode) */
#define MMU_MAP_K_RW (PTE_PBMT_NC | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)

/* RWCB: Cacheable (PMA Mode) - Normal RAM */
#define MMU_MAP_K_RWCB (PTE_PBMT_PMA | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)

/*
* User Mappings
*/
/* User RW: Non-Cacheable */
#define MMU_MAP_U_RW (PTE_PBMT_NC | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)

/* User RWCB: Cacheable */
#define MMU_MAP_U_RWCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)

/* User ROCB: Cacheable */
#define MMU_MAP_U_ROCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_READONLY | PTE_V)

/* User RWCB: Cacheable */
#define MMU_MAP_U_RWCB_XN (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_XN | PTE_V)

/* Early Mapping: Cacheable */
#define MMU_MAP_EARLY \
PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_PBMT_PMA)
#else
#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
Expand All @@ -99,6 +159,8 @@
#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_EARLY \
PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
#endif

#define MMU_MAP_TRACE(attr) (attr)

#define PTE_XWR_MASK 0xe
Expand Down
20 changes: 8 additions & 12 deletions libcpu/risc-v/t-head/c908/riscv_mmu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,22 +23,27 @@
#if !CONFIG_XUANTIE_SVPBMT
/*
* RISC-V Standard Svpbmt Extension (Bit 61-62)
* 00: PMA (Normal Memory, Cacheable)
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
* 01: NC (Non-cacheable, Weakly-ordered)
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
* 11: Reserved
*/
#define PTE_PBMT_MASK (3UL << 61)
#define PTE_PBMT_PMA (0UL << 61)
#define PTE_PBMT_NC (1UL << 61)
#define PTE_PBMT_IO (2UL << 61)
#define PTE_PBMT_MASK (3UL << 61)
#else
/* XuanTie Extension (Bit 59-63) */
#define PTE_SEC (1UL << 59) /* Security */
#define PTE_SHARE (1UL << 60) /* Shareable */
#define PTE_BUF (1UL << 61) /* Bufferable */
#define PTE_CACHE (1UL << 62) /* Cacheable */
#define PTE_SO (1UL << 63) /* Strong Order */
/* Compatible with Standard Svpbmt */
#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
#endif

#define PAGE_OFFSET_SHIFT 0
Expand Down Expand Up @@ -82,22 +87,13 @@
*/
#define PAGE_DEFAULT_ATTR_LEAF \
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)

/*
* Next Level Attribute:
* Svpbmt spec requires PBMT bits to be 0 for non-leaf PTEs.
*/
#define PAGE_DEFAULT_ATTR_NEXT \
(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_A | PTE_D)
#else
#define PAGE_DEFAULT_ATTR_LEAF \
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | \
PTE_CACHE | PTE_A | PTE_D)

#define PAGE_DEFAULT_ATTR_NEXT \
(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D)
#endif

#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)

#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
Expand Down
12 changes: 12 additions & 0 deletions libcpu/risc-v/virt64/riscv_mmu.h
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Expand Up @@ -18,6 +18,18 @@

#undef PAGE_SIZE

/*
* RISC-V Standard Svpbmt Extension (Bit 61-62)
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
* 01: NC (Non-cacheable, Weakly-ordered)
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
* 11: Reserved
*/
#define PTE_PBMT_PMA (0UL << 61)
#define PTE_PBMT_NC (1UL << 61)
#define PTE_PBMT_IO (2UL << 61)
#define PTE_PBMT_MASK (3UL << 61)

#define PAGE_OFFSET_SHIFT 0
#define PAGE_OFFSET_BIT 12
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
Expand Down