microcontroller/Microcontroller.adf at master · evallen/microcontroller · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
[Project]
Current Flow=Generic
VCS=0
version=3
Current Config=compile

[Configurations]
compile=Microcontroller

[Library]
Microcontroller=.\Microcontroller\Microcontroller.lib

[Settings]
AccessRead=0
AccessReadWrite=0
AccessACCB=0
AccessACCR=0
AccessReadWriteSLP=0
AccessReadTopLevel=1
DisableC=1
ENABLE_ADV_DATAFLOW=0
FLOW_TYPE=HDL
LANGUAGE=VHDL
FLOWTOOLS=NONE
REFRESH_FLOW=1
FAMILY=
fileopenfolder=C:\My_Aldec_Designs\test_workspace\Microcontroller\src

[LocalVerilogSets]
EnableSLP=1
EnableDebug=0

[LocalVhdlSets]
CompileWithDebug=0

[$LibMap$]
Microcontroller=.
Active_lib=

[SpecTracer]
WindowVisible=0

[HierarchyViewer]
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=

[Folders]
Name3=Makefiles
Directory3=c:\My_Aldec_Designs\test_workspace\Microcontroller\
Extension3=mak
Name4=Memory
Directory4=c:\My_Aldec_Designs\test_workspace\Microcontroller\
Extension4=mem;mif;hex
Name5=Dll Libraries
Directory5=c:\My_Aldec_Designs\test_workspace\Microcontroller\
Extension5=dll
Name6=PDF
Directory6=c:\My_Aldec_Designs\test_workspace\Microcontroller\
Extension6=pdf
Name7=HTML
Directory7=c:\My_Aldec_Designs\test_workspace\Microcontroller\
Extension7=htm;html

[Groups]
TestBench=1

[Files]
/memory.vhd=-1
/microcontroller_package.vhd=-1
/register_file.vhd=-1
/cpu.vhd=-1
/register_file_test.asdb=-1
/register_file_test.awc=-1
/alu_test.asdb=-1
/alu_test.awc=-1
/initial_ROM.txt=-1
/initial_RAM.txt=-1
/memory_test.asdb=-1
/memory_test.awc=-1
/instruction_fetch_LUT.vhd=-1
/control_unit.vhd=-1
/integration_test.asdb=-1
/integration_test.awc=-1
/alu.vhd=-1
TestBench/cpu_TB.vhd=-1
TestBench/register_file_TB.vhd=-1
TestBench/memory_TB.vhd=-1
TestBench/register_file_TB_runtest.do=-1
TestBench/alu_TB.vhd=-1
TestBench/alu_TB_runtest.do=-1
TestBench/cpu_TB_runtest.do=-1
TestBench/memory_TB_runtest.do=-1
TestBench/instruction_fetch_lut_TB.vhd=-1
TestBench/instruction_fetch_lut_TB_runtest.do=-1

[Files.Data]
.\src\memory.vhd=VHDL Source Code
.\src\microcontroller_package.vhd=VHDL Source Code
.\src\register_file.vhd=VHDL Source Code
.\src\cpu.vhd=VHDL Source Code
.\src\register_file_test.asdb=Accelerated Waveform File
.\src\register_file_test.awc=Accelerated Waveform Configuration
.\src\alu_test.asdb=Accelerated Waveform File
.\src\alu_test.awc=Accelerated Waveform Configuration
.\src\initial_ROM.txt=Text File
.\src\initial_RAM.txt=Text File
.\src\memory_test.asdb=Accelerated Waveform File
.\src\memory_test.awc=Accelerated Waveform Configuration
.\src\instruction_fetch_LUT.vhd=VHDL Source Code
.\src\control_unit.vhd=VHDL Source Code
.\src\integration_test.asdb=Accelerated Waveform File
.\src\integration_test.awc=Accelerated Waveform Configuration
.\src\alu.vhd=VHDL Source Code
.\src\TestBench\cpu_TB.vhd=VHDL Test Bench
.\src\TestBench\register_file_TB.vhd=VHDL Test Bench
.\src\TestBench\memory_TB.vhd=VHDL Test Bench
.\src\TestBench\register_file_TB_runtest.do=Macro
.\src\TestBench\alu_TB.vhd=VHDL Test Bench
.\src\TestBench\alu_TB_runtest.do=Macro
.\src\TestBench\cpu_TB_runtest.do=Macro
.\src\TestBench\memory_TB_runtest.do=Macro
.\src\TestBench\instruction_fetch_lut_TB.vhd=VHDL Test Bench
.\src\TestBench\instruction_fetch_lut_TB_runtest.do=Macro